AMD plans cache-heavy Venice-X server chips for 2027 rollout

AMD is reviving its cache-packed Epyc X server processors with Venice-X, designed for high-performance computing and technical workloads where quick access to data matters. The chips combine large caches with higher clock speeds, addressing a trade-off that constrained earlier generations, and could broaden their use in fields such as electronic design automation and scientific computing.

Venice-X is expected to begin shipping in the second half of 2027, with up to 96 cores and more than 1GB of L3 cache per socket. Its eight CPU chiplets can each pair with a 96MB SRAM tile, delivering up to 1,152MB of L3 cache, while clock speeds reach 5.3GHz, compared with 3.7GHz for Genoa-X. AMD says moving the SRAM beneath the compute chiplets helps reduce heat constraints; its previous Epyc X generation launched in 2023, and the company says enterprise HPC demand follows a slower upgrade cycle.