AMD’s upcoming Zen 6-based Epyc “Venice” processors represent the company’s largest CPU architecture shift since 2019’s Rome generation. The range is intended to span general-purpose computing, enterprise workloads, high-performance computing and AI, with the new chips positioning AMD to challenge Nvidia’s growing influence in data-centre processors.

The Epyc 9006 SP7 platform is expected to launch in 2026 with up to 256 cores, 16 DDR5 memory channels and 128 lanes of PCIe 6.0 connectivity compatible with CXL 3.1. Venice will include density-optimised and frequency-optimised variants: the former can reach 256 cores, while the latter is expected to offer up to 96 cores and boost to 5GHz. AMD has doubled compute cores per chiplet to 32 and increased shared L3 cache to 128MB per chiplet, potentially providing up to 1GB of L3 cache; unlike earlier generations, Zen 6 and compact Zen 6C cores appear to share the same architecture and cache allocation, differing mainly in clock speed and density.